Semiconductor devices, for example, dynamic random access memory (DRAM) devices, are shrinking in the sense that smaller devices are being manufactured that are able to handle larger volumes of data at faster data transfer rates. As a result, semiconductor manufacturers are moving toward chip-scale packages (CSP) for semiconductor components which have a small size and fine pitch wiring.
Exemplary CSPs are shown in FIGS. 1 and 2 as a flip-chip-in-package-board-on-chip (FCIP-BOC) package 10 and a board-on-chip BOC package 50, respectively. Each of the packages comprises a semiconductor component 12 (such as, for example, an integrated circuit (IC) chip), and can thus be referred to as semiconductor packages.
The packages 10 and 50 also comprise an interposer 14 utilized to support the semiconductor component 12. The shown interposer is a board, and such board would typically be a glass weave material. In the case of BOC construction 50, chip 12 is attached to board 14 through an adhesive 16. In the case of FCIP-BOC construction 10, the attachment between the chip 12 and board 14 is through a series of electrical contacts 18 and/or 36. Each of the illustrated contacts 18 comprises an electrically conductive interconnect material 20 (shown as a small ball) between a pair of contact pads 22 and 24. The contact pad 22 is associated with chip 12, and the contact pad 24 is associated with board 14. Contact pad 24 will typically comprise a stack of a copper layer, nickel layer and gold layer; with the copper layer being adjacent board 14 and the gold layer being adjacent ball 20 of interconnect 18. Contact pads 22 can comprise constructions analogous to those of contact pads 24.
Constructions 10 and 50 are shown comprising contact pads 30 on an underside of the board 14 (i.e., on a side of board 14 in opposing relation relative to the side proximate chip 12), and comprising electrically conductive interconnect material (shown as solder balls 32) on the contact pads 30. Contact pads 30 can comprise constructions analogous to those described above with reference to pads 24, and accordingly can comprise stacks of copper, nickel and gold. Solder balls 32 are utilized to form electrical interconnections between contact pads 30 and other circuitry (not shown) external of the chip package (i.e., the package 10 or the package 50).
The boards 14 have orifices 34 extending therethrough. Wire bonds 36 extend from contact pads 38 associated with chips 12 to contact pads 40 associated with an underside of board 14. The contact pads 40 can be connected with pads 30 through circuit traces (not shown in the views of FIGS. 1 and 2). The FCIP-BOC construction 10 also comprises conductive vias 42 extending through board 14 to connect selected contact pads 24 above the board with selected contact pads 30 beneath the board.
Suitable encapsulant 44 can be provided over the chip 12, around the wire bonds 36, and within orifice 34 as shown.
From the discussion above it can be recognized that FCIP-BOC construction 10 is similar to BOC construction 50, with the primary differences being that FCIP-BOC construction 10 comprises contacts formed both above and below board 14 (i.e., on opposing surfaces of board 14), whereas BOC construction 50 has contacts formed only beneath board 14.
The invention described herein includes methods of forming boards and other interposers utilized in semiconductor packages. The methods can be utilized in, for example, forming either FCIP-BOC constructions or BOC constructions. Before discussing the methods of the present invention, a problem associated with prior art fabrication of boards is described with reference to FIGS. 3-9. The figures show an exemplary process for forming a board of a BOC construction, but it is to be understood that similar methodology is utilized for forming boards utilized in FCIP-BOC constructions, and accordingly problems similar to those described with reference to FIGS. 3-9 also occur in forming boards associated with FCIP-BOC constructions.
Referring to FIGS. 3 and 4, a construction 51 is shown at a preliminary stage of a prior art process of fabricating the board for utilization in a BOC construction. The construction is shown in a cross-sectional view in FIG. 3, and in a top view in FIG. 4.
Construction 51 includes a board 14. Board 14 comprises a first surface 15 and a second surface 17 in opposing relation to first surface 15. A conductive layer 52 is provided over first surface 15. Conductive layer 52 will typically comprise, for example, copper, and can have an initial thickness of greater than 10 microns, with a typical thickness being about 12 microns. Since the shown board is to be utilized for forming a BOC construction, conductive layer 52 is only along one of the surfaces 15 and 17. However, if board 14 were to be utilized in forming a FCIP-BOC construction, the conductive material would be formed along both of surfaces 15 and 17.
FIGS. 5 and 6 show construction 51 at a processing stage subsequent to that of FIGS. 3 and 4 along cross-sectional and top views, respectively. Layer 52 is patterned into a series of circuit traces 54. It is noted that an alternative route to obtain the construction of FIGS. 5 and 6, other than that shown in FIGS. 3-6, is to start with a construction having conductive material 52 over both of opposing sides 15 and 17 at the processing stage of FIG. 3, and to etch the conductive material from over side 17 while forming the traces 54 of FIGS. 5 and 6.
FIGS. 7 and 8 show construction 51 at a processing stage subsequent to that of FIGS. 5 and 6, along cross-sectional and top views, respectively. A series of conductive busses 56 (shown in FIG. 8) are formed across upper surface 15 of board 14, and utilized to form electrical connections to traces 54. Subsequently, a patterned mask (not shown) is formed over portions of traces 54 while leaving portions 62 exposed for formation of contact pads 30. Contact pads are formed electrolytically. Specifically, busses 56 are connected to a power source (not shown), and subsequently conductive layers 58 and 60 are plated onto the contact pad locations of traces 54 to form the contact pads 30. Layers 58 and 60 can comprise, consist essentially of, or consist of, for example, nickel and gold, respectively; and can be referred to as a nickel-containing layer and a gold-containing layer, respectively.
FIG. 9 shows a top view of construction 51 in a processing stage subsequent to that of FIG. 8. Specifically, orifice 34 has been formed to extend through board 14. Orifice 34 can be formed utilizing, for example, a router. The forming of orifice 34 removes the majority of busses 56 from board 14. However, remaining portions of busses 56 can problematically leave burrs 70 along edges of orifice 34. Also, the busses can have a so-called “antenna effect” on high speed traces, which can impair high frequency electrical performance.
Other problems of prior art processes of forming conductive traces and contact pads for board substrates can include utilization of unstable plating solutions, poor wirebondability, slow plating processes, difficulty in achieving thick platings, and high cost due to, among other things, complexities of incorporating busses into design space.
In light of the above-discussed problems, it is desirable to develop new methods of forming interposers suitable for incorporation into semiconductor packages.